Horizontal diversity in test generation for high fault coverage

High-Level Test Generation for Gate-Level Fault Coverage

In this paper we introduce a spectral method of register transfer level (RTL) test generation for sequential circuits. We define RTL faults as stuck-at faults on all primary inputs, primary outputs, and flip-flop terminals. Test vectors generated to cover the RTL faults are analyzed using Hadamard matrices. The analysis determines the amplitudes of prominent Walsh functions and the random noise...

Incremental Test Generation Guided by Fault Coverage

Test Generation for CEFSM Combining Specification and Fault Coverage

We discuss how specification coverage and fault coverage based test derivation strategies can be combined. In particular, the problem of deriving a test suffix, which raises tester confidence in the configuration of the system, reached after a test derived by a specification coverage criterion, is formalized and solved in the CEFSM setting. The traditional mutant-based test derivation approach ...

High Fault Coverage Built-In Self-Test for 3 Generation Mobile Phone User

On-chip Built-In Self-Test (BIST) based implementation on RF devices especially on cellular mobile phone has been proposed. In this approach, high-level functional test can be done with one complete test path. Central baseband processor roles as Test Pattern Generator (TPG) as well as Output Response Analyzer so that it can generate test patterns through the complete path over the transceiver c...

Automatic Generation of High Coverage Transient Fault Detectors Using Goldmine

We propose a formal technique for automatic generation of tran­ sient fault detectors for flip-flops/latches in control logic. We apply GoldMine, an automatic assertion generation engine based on data mining and formal verification to generation of fault detectors. The GoldMine tool flow is modified to include fault coverage evalu­ ation of assertions. Our formal technique is sound and complete...